Manufacturers of semiconductor chip packages use encapsulation to protect the silicon die and delicate wire bonded leads of the devices from moisture, chemical attack and mechanical stresses. With recent advances in chip packaging technology, such as in micro-ball gate array (".mu.pBGA") chip packaging, the encapsulant material also serves as a compliant or resilient layer between the silicon die and the support substrate to accommodate for differences in the thermal coefficient of expansion of the die and support substrate.
In .mu.BGA chip packaging, the silicon die is not bonded directly to the substrate as in other chip packaging schemes, but rather is supported above the substrate by compliant standoffs that create a small gap or void between the die and the support substrate. Wire bonded leads extend from the support substrate and are attached to contacts formed on the surface of the silicon die that faces the substrate. The encapsulant material is forced into the gap between the die and substrate to fill voids formed between the wire bonded leads and compliant standoffs, as well as to isolate the die surface and contacts from the outside environment. The encapsulant layer has sufficient resiliency to absorb the mechanical stresses created between the die and substrate that result from the mismatched thermal coefficients of expansion.
In the past, manufacturers of .mu.BGA chip packages and other types of chip packages have used pressure encapsulation to create a void-free encapsulation layer between the die and substrate. In this technique, encapsulant material is dispensed onto the substrate about three peripheral edges of the die. Capillary action pulls the encapsulant material beneath the die into the gap. After some dwell time to allow the material to flow beneath the die, material is dispensed along the fourth edge of the die to create a trapped void beneath the die. The chip package is placed in a pressure oven and subjected to an increased pressure over atmosphere. The pressure differential created between the trapped void and the surrounding chamber collapses the void and forces encapsulant material to uniformly fill the gap between the die and support substrate.
Recently, vacuum encapsulation has been developed to form void-free encapsulation layers in .mu.BGAs and other chip packages. Examples of vacuum encapsulation systems and methods may be found in U.S. Pat. Nos. 5,659,952 and 5,203,076.
In any encapsulation dispensing process, several critical issues must be addressed, including the elimination of any voids or bubbles in the dispensed encapsulant layer, as well as the speed of the encapsulation process. Currently, there is still a need to improve the speed of the encapsulation process, especially for high-volume chip scale manufacturers.